This invention relates generally to non-volatile semiconductor memories of the flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, particularly to structures and methods of operating NAND types of memory cell arrays. All patents, patent applications and other material cited in the present application are hereby incorporated by reference in their entirety.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells.
An example memory system is illustrated by the block diagram of FIG. 1. A memory cell array 1 including a plurality of memory cells arranged in a matrix is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5. The memory cell array 1 is, in this example, a NAND type flash memory array. A control circuit 2 is connected to bit lines (BL) of the memory cell array 1 for reading data stored in the memory cell, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines (BL) to promote the programming or to inhibit the programming. The row control Circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply program voltages combined with the bit line potential levels controlled by the column control circuit 2, and to apply an erase voltage coupled with a voltage of a p-type region (cell P-well) on which the memory cells are formed. The c-source control circuit 4 controls a common source line connected to the memory cells. The c-p-well control circuit 5 controls the cell P-well voltage.
The data stored in the memory cells are read out by the column control circuit 2 and are output to external I/O lines via an I/O line and a data input/output buffer 6. Program data to be stored in the memory cells are input to the data input-output buffer 6 via the external I/O lines, and transferred to the column control circuit 2. The external I/O lines are connected to a controller 9. The controller 9 includes various types of registers and other memory including a volatile random-access-memory (RAM) 10.
Command data for controlling the flash memory device are inputted to command circuits 7 connected to external control lines that are connected with the controller 9. The command data informs the flash memory of what operation is requested. The input command is transferred to a state machine 8 that controls the column control circuit 2, the row control circuit 3, the c-source control circuit 4, the c-p-well control circuit 5 and the data input/output buffer 6. The state machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
The controller 9 is connected or connectable with a host system such as a personal computer, a digital camera, or a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from the memory array 1, and provides or receives such data, respectively. The controller converts such commands into command signals that can be interpreted and executed by the command circuits 7. The controller also typically contains buffer memory for the user data being written to or read from the memory array. A typical memory system includes one integrated circuit chip 11A that includes the controller 9, and one or more integrated circuit chips 11B that each contains a memory array and associated control, input/output and state machine circuits. It is possible to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips.
The memory system of FIG. 1 may be embedded as part of the host system, or may be included in a memory card that is removably insertible into a mating socket of a host system. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards. Several card implementations are described, for example, in U.S. Pat. No. 5,887,145, which patent is expressly incorporated herein in its entirety by this reference.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. BL0-BL4 (of which BL1-BL3 are also labeled 12-16) represent diffused bit line connections to global vertical metal bit lines (not shown). Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 (labeled P2 in FIG. 2B, a cross-sectional along line A-A of FIG. 2A) and string selection lines SGD and SGS extend across multiple strings over rows of floating gates, often in polysilicon (labeled P1 in FIG. 2B). However, for transistors 40 and 50, the control gate and floating gate may be electrically connected (not shown). The control gate lines are typically formed over the floating gates as a self-aligned stack, and are capacitively coupled with each other through an intermediate dielectric layer 19, as shown in FIG. 2B. The top and bottom of the string connect to the bit line and a common source line respectively, commonly through a transistor using the floating gate material (P1) as its active gate electrically driven from the periphery. This capacitive coupling between the floating gate and the control gate allows the voltage of the floating gate to be raised by increasing the voltage on the control gate coupled thereto. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on by placing a relatively high voltage on their respective word lines and by placing a relatively lower voltage on the one selected word line so that the current flowing through each string is primarily dependent only upon the level of charge stored in the addressed cell below the selected word line. That current typically is sensed for a large number of strings in parallel, thereby to read charge level states along a row of floating gates in parallel.
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. Patents/Patent Applications, all of which are incorporated herein by reference: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935, 6,456,528 and 6,522,580.
The charge storage elements of current flash EEPROM arrays are most commonly electrically conductive floating gates, typically formed from doped polysilicon material. However, other materials with charge storing capabilities, that are not necessarily electrically conductive, can be used as well. An example of such an alternative material is silicon nitride. Such a cell is described in an article by Takaaki Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501.
Memory cells of a typical non-volatile flash array are divided into discrete blocks of cells that are erased together. That is, the block contains the minimum number of cells that are separately erasable together as an erase unit, although more than one block may be erased in a single erasing operation. Each block typically stores one or more pages of data, a page defined as the minimum number of cells that are simultaneously subjected to a data programming and read operation as the basic unit of programming and reading, although more than one page may be programmed or read in a single operation. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example is a sector of 512 byes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which it is stored.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. Another way to increase the storage density of data is to store more than one bit of data per memory cell charge storage element. This is accomplished by dividing the allowable voltage or charge storage window of a charge storage element into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operating is described in U.S. Pat. Nos. 5,043,940; 5,172,338, 5,570,315 and 6,046,935.
A typical architecture for a flash memory system using a NAND structure will include NAND arrays, where each array includes several NAND strings. For example, FIG. 3A shows only three NAND strings 11, 13 and 15 of the memory array of FIG. 2A, which array contains more than three NAND strings. Each of the NAND strings of FIG. 3A includes two select transistors and four memory cells. For example, NAND string 11 includes select transistors 20 and 30, and memory cells 22, 24, 26 and 28. NAND string 13 includes select transistors 40 and 50, and memory cells 42, 44, 46 and 48. Each string is connected to the source line by its select transistor (e.g. select transistor 30 and select transistor 50). A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by select transistors 20, 40, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cell 22 and memory cell 42. Word line WL2 is connected to the control gates for memory cell 24 and memory cell 44. Word line WL1 is connected to the control gates for memory cell 26 and memory cell 46. Word line WL0 is connected to the control gates for memory cell 28 and memory cell 48. As can be seen, each bit line and the NAND strings connected to it form the columns of the array of memory cells. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. For example, word line WL2 is connected to the control gates for memory cells 24, 44, and 64.
FIG. 3B is a circuit diagram depicting a number of NAND strings, with each string in a block controlled by a set of common word lines. A block is the unit of erase of a NAND memory array. Strings that share a common set of word lines and source and drain select lines form a block in the NAND design of FIGS. 2A-3B. Strings 11, 13 of FIGS. 2A and 3A-3B appear in a block in FIG. 3B, along with other strings. As shown in FIG. 3B, each NAND string (e.g. 11, 13) in the same array is connected to one of a plurality of bit lines 12, 14, . . . and to a common source line, and are controlled by a common set of word lines (WL0-WL3).
Each memory cell can store data (analog or digital). When storing one bit of digital data (binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0”. In one example of a NAND type flash memory, the threshold voltage is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after a program operation is positive and defined as logic “0.” When the threshold voltage is negative and a read is attempted with 0 volt applied to its control gate, the memory cell will conduct current to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on, which indicates that logic zero is stored. A memory cell can also store multiple levels of information, for example, multiple bits of digital data. In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information are stored, there will be four threshold voltage ranges, each range assigned to one data value. Memories storing data by differentiation between multiple (i.e. more than two) ranges of threshold voltage are known as multiple state memories. In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as “11”. Positive threshold voltages are used for the states of “10”, “01”, and “00.”
When programming a NAND flash memory cell, a program voltage is applied to the control gate and the channel area of the NAND string that is selected for programming is grounded (0V). Electrons from the channel area under the NAND string are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the cell is raised. To ground the channel area of the selected NAND string, the corresponding bitline is grounded (0 volt), while the SGD is connected to a sufficiently high voltage (typically Vdd at for example 3.3 volts) that is higher than the threshold voltage of the select transistors. To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one cell in each of the other NAND strings that utilize the same word line. For example, when programming cell 24 of FIG. 3A, the program voltage will also be applied to the control gate of cell 44 because both cells share the same word line. A problem arises when it is desired to program one cell on a word line without programming other cells connected to the same word line, for example, when it is desired to program cell 24 and not cell 44. Because the program voltage is applied to all cells connected to a word line, an unselected cell (a cell that is not to be programmed) on the word line may become inadvertently programmed. For example, cell 44 is adjacent to cell 24. When programming cell 24, there is a concern that cell 44 might unintentionally be programmed. The unintentional programming of the unselected cell on the selected word line is referred to as “program disturb.” More generally speaking, “program disturb” is used to describe any unwanted threshold voltage shift, either in the positive or negative direction, which can occur during a programming operation and is not necessarily limited to the selected word line.
Several techniques can be employed to prevent program disturb. One method known as “self boosting” (“SB”) is proposed by K. D. Suh et al. in “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” Journal of Solid-State Circuits, Vol 30, No. 11, November 1995, pp. 1149-55. During programming using the SB scheme, the channel areas of the unselected NAND strings are electrically isolated from their corresponding bit lines. Subsequently an intermediate pass voltage (e.g. 10 volts) is applied to the unselected word lines while a high program voltage (e.g. 18 volts) is applied to the selected word line. In this application, the terms “isolate” and “electrically isolate” are used interchangeably, and the terms “writing voltage,” “program voltage” and ‘programming voltage” are used interchangeably. The channel areas of the unselected NAND strings are capacitively coupled to the unselected word lines, causing a voltage (e.g. six volts, assuming a coupling ratio of 0.6) to exist in the channel areas of the unselected NAND strings. This so called “Self Boosting” reduces the potential difference between the channel areas of the unselected NAND strings and the program voltage that is applied to the selected word line. As a result, for the memory cells in the unselected NAND strings and especially for the memory cells in such strings on the selected word line, the voltage across the tunnel oxide and hence the program disturb are significantly reduced.
Referring to FIG. 3A, when a self boosting program technique is applied to the memory array in FIG. 3A to program one of the cells on bit line 12, for example, zero volt is applied to the bit line 12 and voltage Vdd (e.g. 3.3 volts) is applied to the bit line 14. The voltage Vdd is applied to the drain select line SGD to turn on the transistors 20 and 40 and zero volt is applied to the source select line SGS to turn off transistors 30 and 50. Assuming that all of the memory cells in the array 42-48 are in the normally on states (e.g. erased or negative threshold voltage state), the channel potential of all the cells in the NAND string between transistors 40 and 50 is given by the difference between Vdd applied to SGD and the threshold voltage of the select transistor 40. For example, if Vdd is 3.3 volts and the threshold voltage of transistor 40 is 1.3 volts, then the channel potential of all the cells 42-48 is charged to 2 volts. The above operation can be referred to as “pre-charging” since the channel potential is pre-charged to a predefined potential of about 2V in this case. Since transistor 50 is turned off and transistor 40 will turn off automatically after the channel potential of the NAND string has reached a sufficiently high value (2V in this case) the channel potential of memory cells 42-48 becomes floating. Therefore, when the high program voltage Vpgrn (e.g. 18 volts) is applied to the word line WL2, and an intermediate voltage Vpass (e.g. 10 volts) is applied to the remaining word lines, the channel potential of memory cells 42-48 is bootstrapped or boosted from 2 volts, the initial pre-charged level, to a value such as 8 volts, due to capacitive coupling, assuming a coupling ratio of about 0.6. Therefore, even though a high voltage such as 18 volts is applied to the control gate of memory cell 44, the potential difference between such high voltage and the channel potential is not adequate to cause electron tunneling through the oxide to the floating gate of memory cell 44, thereby preventing program disturb. One problem that may occur during self-boosting is “boosting voltage disturb,” (or “Vpass disturb”) where the application of Vpass to word lines causes some charging of floating gates under those word lines. Though Vpass is generally chosen to be low (about 10 volts), some charging may occur, especially after repeated application of Vpass to a word line during programming of other word lines. A higher value of Vpass may provide a higher channel voltage for program inhibited strings and thereby allow a lower value of Vpgm to be used, resulting in less Vpgm-disturb. However, higher Vpass results in more boosting voltage disturb. Thus, there is generally a tradeoff in selecting a value for Vpass.
A NAND string is typically (but not always) programmed from the source side to the drain side, for example, from memory cell 28 to memory cell 22. When the programming process is ready to program the last (or near the last) memory cell of the NAND string, if all or most of the previously programmed cells on the string being inhibited (e.g. string 13) were programmed, then there is negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the pre-charging cannot take place completely, resulting in a lower initial potential of the channel area under the NAND string and the subsequent self-boosting of such channel area becomes less effective as well. Therefore, the boosted potential in the channels of the unselected NAND strings may not become high enough and there still may be program disturb on the last few word lines. For example, when programming voltage is applied to WL3, if cells 48, 46, and 44 on a string that is inhibited were programmed, then each of those memory cells 44, 46, 48 has a negative charge on its floating gate which will limit the boosting level of the self boosting process and possibly cause program disturb on cell 42.
In view of the above problem, as an improvement, T. S. Jung et al. proposed a local self boosting (“LSB”) technique in “A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications”, ISSCC96, Session 2, Flash Memory, Paper TP 2.1, IEEE, pp. 32.
In the LSB scheme, when applying a high programming voltage to the word line WL2, in order to reduce or prevent program disturb in regard to memory cell 44 on a string that is inhibited, an isolating voltage (typically 0 volts) is applied to word lines WL1 and WL3 so that memory cells 42 and 46 are turned off. Then the channel potential in memory cell 44 is then not influenced, or at least less influenced, by the self boosting in the channel regions of memory cells 42, 46, and 48. Therefore, the channel potential of the channel region of memory cell 44 may be self boosted by the high programming voltage Vpgm to a voltage level that is higher than that achieved when the channel region of memory cell 44 is influenced by the self boosting in the remaining memory cells 42, 46, and 48. This prevents program disturb when memory cell 24 is being programmed. For a more detailed explanation of self boosting and local self boosting, please see U.S. Pat. No. 6,107,658, especially the description in columns 6-10.
Another technique proposed as an alternative to local self boosting is described in U.S. Pat. No. 6,525,964 to Tanaka et al. and is known as erased area self boosting (“EASB”). EASB differs from LSB in that, instead of turning off both memory cells on either side of the unselected cell to prevent program disturb of the cell as in LSB, EASB turns off only the memory cell on the source side of the unselected cell. For example, where memory cell 24 is being programmed, only memory cell 46 is being turned off without turning off memory cell 42, in order to prevent program disturb at cell 44. Thus, an isolating voltage is supplied to the neighboring word line on the source side of the selected word line.
One problem with both LSB and EASB techniques occurs when a low isolating voltage is generally applied to adjacent word lines on both sides (LSB) or an adjacent word line on one side (EASB). Such a low voltage (e.g. 0 volts) may affect the voltage of a floating gate that is to be programmed. FIG. 4A shows a cross section of a NAND string during LSB programming of a row of memory cells under word line WLn. Capacitive coupling between floating gate FGn and adjacent word lines WLn−1 and WLn+1 is also shown in FIG. 4A. FIG. 4B shows the voltages supplied to word lines WLn−3 to WLn+3 during programming of cells along word line WLn (i.e. when WLn is the selected word line). As shown in FIG. 4B, the word lines immediately adjacent to word line WLn, word lines WLn−1 and WLn+1, receive an isolating voltage (Viso) to cause memory cells under WLn−1 and WLn+1 to turn off, thus isolating the portion of the substrate under WLn. However, the voltages on word lines WLn−1 and WLn+1 are capacitively coupled to floating gates under adjacent word lines. In particular, voltages on word lines WLn−1 and WLn+1 are capacitively coupled to floating gate FGn, a floating gate under selected word line WLn. In this example, floating gate FGn is being programmed, so the channel under floating gate FGn is held at a low voltage (typically 0 volts). In order to cause electrons to tunnel through the gate oxide layer into floating gate FGn, the voltage of floating gate FGn is raised to a high voltage by applying a programming voltage (about 18-20 volts) on word line WLn. However, the low isolation voltages on WLn−1 and WLn+1 coupled to floating gate FGn make this more difficult. These low voltages tend to counteract the coupling of high voltage Vpgm from word line WLn. The result is that a voltage used for Vpgm may be higher than desired, increasing disturb problems in other floating gates. Also, programming may take longer than it would if it were not for the coupling of low voltages by word lines WLn−1 and WLn+1. While FIGS. 4A and 4B show the problem for the LSB situation, the problem also occurs in EASB schemes, though only on one side of the selected word line.
While LSB and EASB maybe advantageous for many applications, certain problems are still encountered when these schemes are used in their current form, especially when the memory cell dimensions of future generation devices are continually reduced or scaled down. In particular, as memory arrays are reduced in size, not all dimensions are reduced in proportion. Typically, in a NAND flash memory such as shown in FIG. 4A, the Inter Poly Dielectric (IPD) layer that separates word lines from underlying floating gates is not reduced in proportion to a reduction in spacing between adjacent word lines or floating gates. Thus, as an array shrinks, the coupling between WLn−1 and FGn increases relative to the coupling between WLn and FGn. Thus, the coupling of isolating voltage from word lines adjacent to the selected word line, described above with respect to FIGS. 4A and 4B, generally becomes more significant as memory array dimensions shrink.